Traditionally, in the manufacture of integrated circuits, the contacts to polycrystalline silicon and metal structures, and to diffusion regions, are designed such that a border region is provided surrounding the region where the contact is to be formed. Borders around the contacts are used primarily to ensure that under worst-case conditions, the contact openings will never extend beyond the structure or regions with which contact is to be made. If the border is not used, the contacts, due to normal process variations, may fall partially on the desired structure or regions and partially over adjacent structures or regions, thereby forming undesired connections. When this occurs, the field oxide may be consumed during an over etch and a metal-to-substrate leakage path may be formed. Consumption of the field oxide may also result in over-etching of the silicon substrate.
While borders around contact windows ensure proper registration of the contacts and protection of the underlying conductive structures, they have the undesirable effect of limiting the maximum number of integrated circuits that can be packed in a given area. By contrast, as the name implies, a borderless contact does not require a border around a contact. Thus, a borderless contact process allows an increased level of circuit integration, and hence an increased IC chip density.
various techniques have been developed for forming borderless contacts, as disclosed in U.S. Pat. No. 4,944,682 to Cronin et al. and U.S. Pat. No. 4,966,870 to Barber et al. The borderless contact processes described in these patents involve depositing a conformal coating of material on a substrate so as to overlie pre-existing topography (e.g., poly-Si interconnect lines or an FET gate stack) and then depositing a second relatively void-free layer of material on top of the first layer. An opening for the borderless contact is formed in the second layer using an etchant that etches the second layer faster than the first layer, with the etch process generally being terminated when the opening extends entirely through the second layer to the first layer. Thus, the first layer serves as an etch stop for the etching process used to form the opening in the second layer. Then, a second etchant is used to extend the opening through the first layer to the selected underlying structure where contact is to be made.
For borderless contact processes of the type disclosed by Cronin et al. and Barber et al. to function effectively, the etching process used to form the opening in the second layer must be highly selective with respect to such layer. That is, the etching process used to etch the opening in the second layer should etch the second layer at a significantly faster rate than the first layer, with etch rate ratios (ERRs) in the range of at least 40:1 being preferred. Unfortunately, the etch selectivity of known etchants that may be used to etch the first and second layers of material deposited using the processes of Cronin et al. and Barber et al. is not, under certain circumstances, as great as is desired. Thus, slight over etching of the second layer can, in certain process sequences, result in the etching of an opening in the first layer as well as an etching of materials underlying the first layer (which typically are not intended to be etched). Thus, a need exists for a borderless contact process involving layers of materials and etching processes that together provide a higher etch selectivity than is typically available with known borderless contact processes.
In connection with the formation of various semiconductor devices, it is known to deposit a first layer of material on a substrate, form openings in the first layer, deposit conductive material in such openings and finally remove the first layer, as disclosed in IBM Technical Disclosure Bulletin, Vol. 14, No. 1, June 1971, U.S. Pat. No. 3,930,857 to Bendz et al. and U.S. Pat. No. 4,359,816 to Abbas et al. However, these known techniques for forming conductive structures in a layer that is subsequently removed are not directed to techniques for forming borderless contacts. Furthermore, these processes do not involve the sequential formation of contacts in the layer of material and then the removal and replacement of material with a different material.
It is known to couple the node electrode of a trench-type capacitor with an adjacent diffusion region using a strap of material extending from the diffusion region to the node electrode, as disclosed in U.S. Pat. No. 5,041,887 to Kumagai et al. Furthermore, techniques have been developed for forming such a strap so that it makes contact both on top of the diffusion region and on a side of the diffusion region intersecting the trench in which the capacitor is formed, as disclosed in IBM Technical Disclosure Bulletin, Vol. 34, No. 7B, December 1991, and European Patent Application No. 201,706 (NEC Corporation).